STPM10 datasheet(16/51 Pages) STMICROELECTRONICS

16 / 51 page

Theory of operation

STPM10

16/51

Doc ID 17728 Rev 3

The gain register is included in the device configuration register with the address name

PST. The table below shows the gain configuration according to the register values:

Note:

If the device is used in configuration PST = 1, TMP = 1 (primary channel with CT, secondary

channel with Shunt), the shunt Ks must always be equal to one fourth of the current

transformer Ks.

Both the voltage and current channels implement an active offset correction architecture

which provides the benefit of avoiding any offset compensation.The analog voltage and

current signals are processed by the

Σ Δ analog-to-digital converters, which feed the hard-

wired DSP. The DSP implements an automatic digital offset cancellation that makes it

possible to avoid any manual offset calibration on the analog inputs.

7.3

ΣΔ A/D converters

Analog-to-digital conversion in the STPM10 is carried out using two first-order

Σ Δ

converters. The device performs A/D conversions of analog signals on two independent

channels in parallel. The current channel is multiplexed as a primary or secondary current

channel in order to perform the tamper function, if enabled. The converted

Σ Δ signals are

supplied to the internal hard-wired DSP unit, which filters and integrates these signals in

order to boost the resolution and to yield all the necessary signals for the computations.

Σ Δ modulator converts the input signal into a continuous serial stream of 1’s and 0’s at a

rate determined by the sampling clock. In the STPM10, the sampling clock is equal to

fCLK/4.

The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is

subtracted from the input signal. If the loop gain is high enough, the average value of the

DAC output (and therefore the bit stream) can approach that of the input signal level. When

a large number of samples are averaged, a very precise value for the analog signal is

obtained. This averaging is carried out in the DSP section, which implements decimation,

Table 6.

Gain of voltage and current channels

Voltage channels

Current channels

Gain

Max input voltage (V)

Gain

Max input voltage (V)

±0.30

±0.15

32X

±0.035

Table 7.

Configuration of current sensors

Primary

Secondary

Configuration

Bits

Configuration

Bits

Gain

Sensor

Gain

Sensor

PST

TMP

Disabled

Shunt

Disabled

8CT0

Shunt

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