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STPMC1 데이터시트(PDF) 32 Page - STMicroelectronics |
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STPMC1 데이터시트(HTML) 32 Page - STMicroelectronics |
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32 / 77 page ![]() Theory of operation STPMC1 32/77 Doc ID 15728 Rev 6 Whatever the SYS bits setting (indicating phases presence and configuration), bit BSF is always calculated, but it is valid only in cases SYS is 0, 1, 2 and 3. In fact in this case all the three phase voltage signals (uR, uS, uT) are available and can be checked, as shown in 0. In cases SYS is 4, 5, 6, 7, only two or one voltage signal are available (uS and/or uT), so that the sequence cannot be checked. Bit BSF is always set in the status byte, but it must be ignored. In standalone application for SYS = 0, 1 or 2 (3-phase systems) bit BSF is available as output on SDATD pin. 9.10.3 Phase active powers do not have the same sign (status bit BIF) The 3-phase status bit BIF is produced from status bit SIGN of each phase. If bit SIGN is not equal in all three phases (R, S and T), then bit BIF is set. In a standalone application for SYS = 0, 1 or 2 (3-phase system) bit BIF is available as output on SDATD pin. Example 9: status bit BIF SIGNR = 0, SIGNS = 0, SIGNT = 0 → BIF = 0 SIGNR = 1, SIGNS = 1, SIGNT = 1 → BIF = 0 SIGNR = 1, SIGNS = 0, SIGNT = 0 → BIF = 1 SIGNR = 0, SIGNS = 1, SIGNT = 0 → BIF = 1 9.10.4 EMI is detected EMI tamper detection is enabled by configuring bits ENH = 1 and APL [1] = 1 (APL [1] sets standalone application mode). The DAH signal is checked to verify that: ● its DC component does not exceed DCMAX/16 ● its RMS value does not exceed the maximum value RMSMAX/16 where DCMAX = RMSMAX = 2 16 with hysteresis. If these condition are not verified the EMI tamper is detected. Table 16. Pin description versus SYS configuration (uX and iX represent the voltage and the current signals) SYS Pin 0 12 34 56 7 DAR uR uR uR uR -- -- DAS uS uS uS uS uS -- - DAT uT uT uT uT uT uT uT uT DAN iN --- -- -- DAR iR iR iR iR -- -- DAS iS iS iS -iS iS iS - DAT iT iT iT iT iT iT iT iT |
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