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DC and AC parameters

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Table 16.

400 kHz AC characteristics

Symbol

Alt.

Parameter

Min.

Max.

Unit

Clock frequency

-

400

kHz

Clock pulse width high

600

-

ns

Clock pulse width low

1300

-

ns

(1)

1.

Characterized only, not tested in production.

SDA (out) fall time

2.

300

ns

Input signal rise time

(3)

3.

There is no min. or max. values for the input signal rise and fall times. It is however recommended by the

I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when

(3)

ns

Input signal fall time

(3)

(3)

ns

Data in set up time

100

-

ns

Data in hold time

0

-

ns

(4)

4.

To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or

rising edge of SDA.

Data out hold time

100

-

ns

(5)

5.

Clock low to next data valid (access time)

-

900

ns

Start condition setup time

600

-

ns

Start condition hold time

600

-

ns

600

-

ns

Time between Stop condition and next Start

condition

1300

-

ns

(6)(1)

6.

WC=0 set up time condition to enable the execution of a WRITE command.

WC set up time (before the Start condition)

0

-

µs

(7)(1)

7.

WC=0 hold time condition to enable the execution of a WRITE command.

WC hold time (after the Stop condition)

1

-

µs

Internal Write cycle duration

-

5

ms

tNS

(1)

Pulse width ignored (input filter on SCL and

SDA) - single glitch

-80

ns