WM8741 datasheet(12/64 Pages) WOLFSON

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WM8741

Production Data

PD, Rev 4.2, October 2009

MASTER CLOCK TIMING

Figure 1 Master Clock Timing Requirements

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Master Clock Timing Information

MCLK Master clock pulse width high

tMCLKH

MCLK Master clock pulse width low

tMCLKL

MCLK Master clock cycle time

tMCLKY

MCLK Duty cycle

40:60

60:40

Table 1 MCLK Timing Requirements

PCM DIGITAL AUDIO INTERFACE TIMINGS

Figure 2 Digital Audio Data Timing

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25

oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

tBCY

BCLK pulse width high

tBCH

BCLK pulse width low

tBCL

LRCLK set-up time to BCLK

rising edge

tLRSU

LRCLK hold time from

BCLK rising edge

tLRH

DIN set-up time to BCLK

rising edge

tDS

DIN hold time from BCLK

rising edge

tDH

Table 2 Digital Audio Interface Timing Requirements

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