WM8750CLSEFLSLASHR datasheet(40/65 Pages) WOLFSON

40 / 65 page

WM8750L

Production Data

PD, Rev 4.4, August 2012

DIGITAL AUDIO INTERFACE

The digital audio interface is used for inputting DAC data into the WM8750L and outputting ADC data

from it. It uses five pins:



ADCDAT: ADC data output



ADCLRC: ADC data alignment clock



DACDAT: DAC data input



DACLRC: DAC data alignment clock



BCLK: Bit clock, for synchronisation

The clock signals BCLK, ADCLRC and DACLRC can be outputs when the WM8750L operates as a

master, or inputs when it is a slave (see Master and Slave Mode Operation, below).

Four different audio data formats are supported:



Left justified



Right justified



DSP mode

All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the

Electrical Characteristic section for timing information.

MASTER AND SLAVE MODE OPERATION

The WM8750L can be configured as either a master or slave mode device. As a master device the

WM8750L generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data

transfer on ADCDAT and DACDAT. In slave mode, the WM8750L responds with data to clocks it

receives over the digital audio interface. The mode can be selected by writing to the MS bit (see

Table 23). Master and slave modes are illustrated below.

BCLK

ADCDAT

ADCLRC

DACDAT

DACLRC

WM8750

CODEC

DSP

ENCODER/

DECODER

Note: The ADC and DAC can run at different sample rates

BCLK

ADCDAT

ADCLRC

DACDAT

DACLRC

WM8750

CODEC

DSP

ENCODER/

DECODER

Note: The ADC and DAC can run at different sample rates

Figure 16 Master Mode

Figure 17 Slave Mode

Note: For optimum ADC audio performance in Slave Mode, the BCLK input signal edge should

coincide with the falling edge of MCLK.

Note that the ADCDAT output pin may be either logic ‘1’ or logic ‘0’ at power-up until data is clocked

out from the ADC. It is recommended to ensure that any external connection to the ADCDAT pin is

compatible with the ADCDAT output pin being driven either high or low by the WM8750L until ADC

data is clocked out. Alternatively, the ADCDAT pin can be tri-stated by setting the TRI bit in Register

R24 (see Table 35).

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