WM8948ECSSLASHR datasheet(108/189 Pages) WOLFSON

부품명	WM8948ECS/R

상세설명	Stereo Low-Power CODEC with Video Buffer and Touch Panel Controller

PDF	189 Pages

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제조업체	WOLFSON [Wolfson Microelectronics plc]

홈페이지	http://www.wolfsonmicro.com

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108 / 189 page

WM8948

Production Data

PD, May 2011, Rev 4.1

108

In Read operations (R/W=1), the SDATA pin is ignored following receipt of the valid register address.

SDOUT is driven by the WM8948.

The 4-wire control mode timing is illustrated in Figure 47 and Figure 48.

Figure 47 4-Wire Readback (CMOS)

Figure 48 4-Wire Readback (Open Drain)

POWER MANAGEMENT

The WM8948 has two control registers that allow users to select which functions are active. For

minimum power consumption, unused functions should be disabled. To minimise pop or click noise,

it is important to enable or disable these functions in the correct order, and to use the signal mute

registers as part of a carefully structured control sequence. Refer to the “Recommended Power

Up/Down Sequence” section for more details.

The power management control registers are described in Table 69.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2 (02h)

Power

management

INPPGAR_ENA

Right Input PGA Enable

0 = Disabled

1 = Enabled

INPPGAL_ENA

Left Input PGA Enable

0 = Disabled

1 = Enabled

WM8948ECS/R 데이터시트(PDF) 108 Page - Wolfson Microelectronics plc