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WM8985GEFL/R 데이터시트(PDF) 40 Page - Wolfson Microelectronics plc |
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WM8985GEFL/R 데이터시트(HTML) 40 Page - Wolfson Microelectronics plc |
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40 / 121 page ![]() WM8985 Production Data w PD, Rev 4.6, July 2009 40 HPFCUT [2:0] SR=101/100 SR=011/010 SR=001/000 fs (kHz) 8 11.025 12 16 22.05 24 32 44.1 48 000 82 113 122 82 113 122 82 113 122 001 102 141 153 102 141 153 102 141 153 010 131 180 196 131 180 196 131 180 196 011 163 225 245 163 225 245 163 225 245 100 204 281 306 204 281 306 204 281 306 101 261 360 392 261 360 392 261 360 392 110 327 450 490 327 450 490 327 450 490 111 408 563 612 408 563 612 408 563 612 Table 16 High Pass Filter Cut-off Frequencies (HPFAPP=1) Note that the High Pass filter values (when HPFAPP=1) are calculated on the assumption that the SR register bits are set correctly for the actual sample rate as shown in Table 16. Sampling rate (SR) is enabled by register bits R7[1:3]. Register 14(0Eh) bits [5:4] (HPFCUT) are used to control the high pass filter cut-off in applications mode and also the PLL output clock division ratio (OPCLKDIV). |
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