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WM8351 데이터시트(PDF) 97 Page - Wolfson Microelectronics plc |
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WM8351 데이터시트(HTML) 97 Page - Wolfson Microelectronics plc |
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97 / 330 page ![]() Production Data WM8351 w PD, April 2012, Rev 4.5 97 8-bit mode is selected whenever DAC_COMP=1 or ADC_COMP=1. The use of 8-bit data allows samples to be passed using as few as 8 BCLK cycles per LRCLK frame. When using DSP mode B, 8-bit data words may be transferred consecutively every 8 BCLK cycles. 8-bit mode (without Companding) may be enabled by setting ADC_COMPMODE=1 when ADC_COMP=0. BIT7 BIT[6:4] BIT[3:0] SIGN EXPONENT MANTISSA Table 50 8-bit Companded Word Composition u-law Companding 0 20 40 60 80 100 120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 39 µ-Law Companding A-law Companding 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1 Normalised Input 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 40 A-Law Companding |
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