Features

PXR40 Product Brief, Rev. 1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

9

— Channel context switch time is six system cycles. Each channel has its own context of static

data memory and timer hardware resources consisting of programmable flags, timer control

and status hardware

— SPRAM shared between host CPU and eTPU, supporting communication either between

channels and host or inter-channel

— Dual-parameter coherency hardware support allows atomic access to two parameters by host

— Enhancements to DMA and interrupt structure to allow any channel to assert any interrupt

•

Test and development support features:

— IEEE-ISTO 5001-2003 standard class 3 compliant for the eTPU (Nexus)

— Data trace via data write messaging and data read messaging

— Ownership trace via ownership trace messaging (OTM)

— Program trace via branch trace messaging

— Watchpoint messaging via the auxiliary port

— SCM continuous signature-check built-in self test (MISC — multiple input signature

calculator), runs concurrently with eTPU normal operation

2.5.7

Software watchdog timer (SWT)

The software watchdog timer (SWT) is a second watchdog module to complement the standard Power

Architecture watchdog integrated in the CPU core. When enabled, the SWT requires periodic execution

of a watchdog servicing sequence. Writing the sequence resets the timer to a specified time-out period. If

this servicing action does not occur before the timer expires the SWT generates an interrupt or hardware

reset. The SWT can be configured to generate a reset or interrupt on an initial time-out, a reset is always

generated on a second consecutive time-out.

The following features are implemented:

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32-bit time-out register to set the time-out period

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Programmable selection of system or oscillator clock for timer operation

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Programmable selection of window mode or regular servicing

•

Programmable selection of reset or interrupt on an initial time-out

•

Master access protection

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Hard and soft configuration lock bits

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Reset configuration inputs allow timer to be enabled out of reset

2.5.8

Periodic interrupt timer (PIT)

The periodic interrupt timer (PIT) is an array of timers that can be used to generate interrupts and trigger

DMA channels. It also provides a dedicated real-time interrupt timer (RTI), which runs on a separate clock

and can be used for system wake-up.