Features

PXR40 Product Brief, Rev. 1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

15

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TCD organized to support two-deep, nested transfer operations

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An inner data transfer loop defined by a “minor” byte transfer count

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An outer data transfer loop defined by a “major” iteration count

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Channel activation via one of three methods:

— Explicit software initiation

— Initiation via a channel-to-channel linking mechanism for continuous transfers

— Peripheral-paced hardware requests (one per channel)

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Support for fixed-priority and round-robin channel arbitration

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Channel completion reported via optional interrupt requests

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One interrupt per channel, optionally asserted at completion of major iteration count

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Error termination interrupts are optionally enabled

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Support for scatter/gather DMA processing

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Channel transfers can be suspended by a higher priority channel

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Nexus data trace support on each DMA

2.5.15

Crossbar switch (XBAR)

The following summarizes the PXR40’s implementation of the crossbar switch:

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Supports simultaneous connections between master ports and slave ports (each master must access

a different slave)

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Supports a 32-bit address bus width and a 64-bit data bus width

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Six master ports:

— e200z7 core complex (two ports)

— eDMA2 module A

— eDMA2 module B

—FlexRay

— Nexus debug interface (NDI)

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Four slave ports

— Flash memory

—SRAM

— Peripheral bridge A

— Peripheral bridge B

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Arbitration logic for when a slave port is simultaneously requested by more than one master

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Includes memory protection unit (MPU) hardware to guard against unintended SRAM or

peripheral accesses by the CPU, eDMA2 modules, and FlexRay module.