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AD6622

–5–

REV. 0

WR (R/W)

RD (DS)

A[2:0]

D[7:0]

RDY

(

DTACK)

tHWR

tSAM

tHAM

tSAM

tHAM

tDRDY

tACC

VALID ADDRESS

VALID DATA

1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF WR TO THE RE OF RDY.

2. tACCFAST REQUIRES A MAXIMUM OF THREE CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 5, 3, 2, 1

3. tACCMEDIUM REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 4 AND 0 IF THE ACCESS IS TO A CONTROL REGISTER

VERSUS A RAM REGISTER.

4. tACCSLOW REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS.

Figure 5. INM Microport Write Timing Requirements

WR (R/W)

RD (DS)

A[2:0]

D[7:0]

RDY

(

DTACK)

tSAM

tACC

VALID ADDRESS

tZD

tDRDY

VALID DATA

tDD

tHA

tZD

1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM THE FE OF WR TO THE RE OF RDY.

2. tACCFAST REQUIRES A MAXIMUM OF THREE CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 5, 3, 2, 1

3. tACCMEDIUM REQUIRES A MAXIMUM OF FOUR CLK PERIODS AND APPLIES TO A[2:0] = 4 AND 0 IF THE ACCESS IS TO A CONTROL REGISTER

VERSUS A RAM REGISTER.

4. tACCSLOW REQUIRES A MAXIMUM OF FIVE CLK PERIODS AND APPLIES TO A[2:0] = 0 WHEN ACCESSING RAM REGISTERS.

Figure 6. INM Microport Read Timing Requirements

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