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RK-Wi.232FHSS-25-FCC-R 데이터시트(PDF) 42 Page - Radiometrix Ltd |
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RK-Wi.232FHSS-25-FCC-R 데이터시트(HTML) 42 Page - Radiometrix Ltd |
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42 / 67 page ![]() WI.232FHSS-25-R/ WI.232FHSS-250-R DATASHEET 41 Revision 1.1.0 4.1.13. UART Acknowledge on Wake (regACKONWAKE) regNVACKONWAKE (0x0E) regACKONWAKE (0x59) R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 7 6 5 4 3 2 1 0 Default UART Acknowledge on Wake: Enabled (0x01) When UART Acknowledge on Wake is enabled, the module will send an ACK (0x06) character out of the UART TxD pin after the module wakes. This indicates that the module is ready to accept data and command traffic. A value of 0x01 enables this feature. Setting the register to 0x00 disables it. 4.1.14. User Destination ID[3] (regUSERDESTID[3]) regNVUSERDESTID[3] (0x0F) regUSERDESTID[3] (0x5A) R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 7 6 5 4 3 2 1 0 Default User Destination ID[3]: 0xFF This is the most significant byte (byte 3) of the 32-bit user extended destination address. When Extended User addressing is enabled, this register is used in conjunction with User Destination Address[2-0] registers to direct a transmitted packet to the proper endpoint(s). For more information on the operation of addressing modes, please refer to the Addressing Modes section of this document. 4.1.15. User Destination ID[2] (regUSERDESTID[2]) regNVUSERDESTID[2] (0x10) regUSERDESTID[2] (0x5B) R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 7 6 5 4 3 2 1 0 Default User Destination ID[2]: 0xFF This is byte 2 of the 32-bit user extended destination address. When Extended User addressing is enabled, this register is used in conjunction with User Destination ID[3] and User Destination ID[1-0] registers to direct a transmitted packet to the proper endpoint(s). For more information on the operation of addressing modes, please refer to the Addressing Modes section of this document. 4.1.16. User Destination ID[1] (regUSERDESTID[1]) regNVUSERDESTID[1] (0x11) regUSERDESTID[1] (0x5C) R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 7 6 5 4 3 2 1 0 |
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