AD775

REV. 0

–6–

DEFINITIONS OF SPECIFICATIONS

Integral Nonlinearity (INL)

Integral nonlinearity refers to the deviation of each individual

code from a line drawn from “zero” through “full scale.” The

point used as “zero” occurs 1/2 LSB before the first code tran-

sition. “Full scale” is defined as a level 1 1/2 LSB beyond the

last code transition. The deviation is measured from the center

of each particular code to the true straight line.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. It is often

specified in terms of the resolution for which no missing codes

(NMC) is guaranteed.

Offset Error

The first code transition should occur at a level 1/2 LSB above

nominal negative full scale. Offset referred to the Bottom of

code transition should occur 1 1/2 LSB below the nominal

defined as the deviation from this ideal.

Differential Gain

The percentage difference between the output amplitudes of a

small high frequency sine wave at two stated levels of a low fre-

quency signal on which it is superimposed.

Differential Phase

The difference in the output phase of a small high frequency

sine wave at two stated levels of a low frequency signal on which

it is superimposed.

Pipeline Delay (Latency)

The number of clock cycles between conversion initiation and

the associated output data being made available. New output

data is provided every clock cycle.

Signal-to-Noise Plus Distortion Ratio (S/N+D)

S/N+D is the ratio of the rms value of the measured input signal

to the rms sum of all other spectral components including har-

monics but excluding dc. The value for S/N+D is expressed in

decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic com-

ponents to the rms value of the measured input signal and is ex-

pressed as a percentage or in decibels.

THEORY OF OPERATION

The AD775 uses a pipelined two-step (subranging) flash archi-

tecture to achieve significantly lower power and lower input

capacitance than conventional full flash converters while still

maintaining high throughput. The analog input is sampled by

the switched capacitor comparators on the falling edge of the

input clock: no external sample and hold is required. The coarse

comparators determine the top four bits (MSBs), and select the

appropriate reference ladder taps for the fine comparators. With

the next falling edge of the clock, the fine comparators determine

the bottom four bits (LSBs). Since the LSB comparators require

a full clock cycle between their sampling instant and their deci-

sion, the converter alternates between two sets of fine compara-

tors in a “ping-pong” fashion. This multiplexing allows a new

input sample to be taken on every falling clock edge, thereby

providing 20 MSPS operation. The data is accumulated in the

correction logic and output through a three-state output latch

on the rising edge of the clock. The latency between input sam-

pling and the corresponding converted output is 2.5 clock cycles.

All three comparator banks utilize the same resistive ladder for

their reference input. The analog input range is determined by

the voltages applied to the bottom and top of the ladder, and

the AD775 can digitize inputs down to 0 V using a single sup-

ply. On-chip application resistors are provided to allow the

ladder to be conveniently biased by the supply voltage.

The AD775 uses switched capacitor autozeroing techniques to

cancel the comparators’ offsets and achieve excellent differential

nonlinearity performance: typically

±0.3 LSB. The integral

nonlinearity is determined by the linearity of the reference lad-

der and is typically +0.5 LSB.

APPLYING THE AD775

REFERENCE INPUT

The AD775 features a resistive reference ladder similar to that

found in most conventional flash converters. The analog input

der is 300 ohms, though this may vary from 230 ohms to 450

linearity performance of the converter may deteriorate for input

earity degradation.

16

23

17

22

325

Ω

90

Ω

300

Ω

AD775

*VALUES FOR

RESISTANCE

ARE TYPICAL

0.1

µF

0.1

µF

Figure 8. Reference Configuration: 0.64 V to 2.73 V

To simplify biasing of the AD775, on-chip reference bias resis-

tors are provided on Pins 16 and 22. The two recommended

configurations for these resistors are shown in Figures 8 and 9.