AD775

REV. 0

–7–

For nominal supply voltages (5 V and 0 V respectively), this

creates an input range of 0.64 V to 2.73 V.

Both top and bottom of the reference ladder should be de-

coupled, preferably with a chip capacitor to ground to minimize

reference noise.

The topology shown in Figure 9 provides a ground-inclusive

16

23

17

22

325

Ω

90

Ω

300

Ω

AD775

*VALUES FOR

RESISTANCE

ARE TYPICAL

0.1

µF

Figure 9. Reference Configuration: 0 V to +2.4 V

More elaborate topologies can be used for those wishing to

provide an input span based on an external reference voltage.

The circuit in Figure 10 uses the AD780 2.5 V reference to

ladder grounded to provide an input span of 0 V to +2.5 V. This is

modified in Figure 11 to shift the 2.5 V span up 700 mV.

16

22

17

23

AD775

NC

NC

NC = NO CONNECT

0.1

µF

AD780

5

6

7

8

NC

NC

NC

1

NC

4

3

2

NC

0.1

µF

+5V

Figure 10. Reference Configuration: 0 V to 2.5 V

The AD775 can accommodate dynamic changes in the reference

voltage for gain or offset adjustment. However, conversions that

are in progress, including those in the converter pipeline, while

the reference voltages are changing will be invalid.

16

22

17

23

AD775

NC

NC

NC = NO CONNECT

0.1

µF

1

3

2

AD822

500pF

10k

Ω

20

Ω

10k

Ω

0.1

µF

7

5

6

AD822

500pF

10k

Ω

20

Ω

10k

Ω

0.1

µF

422

Ω

140

Ω

422

Ω

1

3

2

GND

AD680

0.1

µF

+5V

Figure 11. Reference Configuration: 0.7 V to 3.2 V

ANALOG INPUT

The impedance looking into the analog input is essentially

capacitive, as shown in the equivalent circuit of Figure 12, typi-

cally totalling around 11 pF. A portion of this capacitance is

parasitic; the remainder is part of the switched capacitor struc-

ture of the comparator arrays. The switches close on the rising

edge of the clock, acquire the input voltage, and open on the

clock’s falling edge (the sampling instant). The charge that must

be moved onto the capacitors during acquisition will be a func-

tion of the converter’s previous two samples, but there should be

no sample-to-sample crosstalk so long as ample driving imped-

ance and acquisition time are provided.

SWITCHES EACH

CLOCK CYCLE

C2

SWITCHES ON ALTERNATE

CLOCK CYCLES

C3

C1

C1 + C2 + C3

≈ 11pF

AD775

For example, to ensure accurate acquisition (to 1/4 bit accuracy)

of a full-scale input step in less than 20 ns, a source impedance

of less than 100 ohms is recommended. Figure 13 shows one

option of input buffer circuitry using the AD817. The AD817

acts as both an inverting buffer and level shifting circuit. In

order to level shift the ground-based input signal to the dc level

required by the input of the AD775, the supply voltage is resis-

tively divided to produce the appropriate voltage at the nonin-

verting input of the AD817. For most applications, the AD817

provides a low cost, high performance level shifter. The AD811

is recommended for systems which require faster settling times.