MIPSZ2012D1R0 datasheet(10/48 Pages) PANASONIC

10 / 48 page

AN30183A

Ver. AEB

μs

—

1.3

—

tBUF

Bus free time between STOP

and START condition

μs

—

0.6

—

tSU:STO

Set-up time of STOP condition

300

—

20 +

0.1

× C

—

Fall time of both SDA

and SCL signals

300

—

20 +

0.1

× C

—

Rise time of both SDA

and SCL signals

—

100

—

tSU:DAT

Data set-up time

μs

0.9

—

tHD:DAT

Data hold time

—

0.1

VDVDD

VIO < 2 V,

Hysteresis 2 of SDA, SCL

Vhys2

Hysteresis of Schmitt trigger

input 2

I2C bus (Bus line specifications)

μs

—

0.6

—

tSU:STA

Set-up time for a repeat START

condition

μs

—

0.6

—

tHIGH

High period of the SCL clock

μs

—

1.3

—

tLOW

Low period of the SCL clock

μs

—

0.6

The first clock pulse is

generated after tHD:STA.

tHD:STA

Hold time

(repeated) START condition

—

Capacitance for each I/O pin

—

Tsp

Pulse width of spikes which must

be suppressed by the input filter

I2C bus (Internal I/O stage characteristics)

250

—

20 +

0.1

× C

Bus capacitance : 10 pF to

400 pF

IP ≤ 6mA (VOLmax = 0.6 V)

IP : Max. sink current

Tof

Output fall time from VIHmin to VILmax

—

0.05

VDVDD

VIO > 2 V,

Hysteresis 1 of SDA, SCL

Vhys1

Hysteresis of Schmitt trigger

input 1

Reference values

Typ

Unit

Max

Notes

Min

Conditions

Symbol

Parameter

APPLICATION INFORMATION (Continued)

REFERENCE VALUES FOR DESIGN

VVBAT(DDVBAT1 = VB = VIN2) = 3.1V to 4.5V, DVDD = 1.85V , DC-DC : Co = 4.7 µF, Lo = 1 µH / LDO : Co =1.0 µF

Ta = 25 °C ± 2 °C unless otherwise noted.

Notes)

*2 :Checked by design, not production tested.

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