ADF4116/ADF4117/ADF4118

–19–

REV. 0

INTERFACING

The ADF4116 family has a simple SPI-compatible serial inter-

face for writing to the device. SCLK, SDATA and LE control

the data transfer. When LE (Latch Enable) goes high, the 24 bits

which have been clocked into the input register on each rising

edge of SCLK will get transferred to the appropriate latch. See

Figure 1 for the Timing Diagram and Table II for the Latch

Truth Table.

ADF4116/

ADF4117/

ADF4118

10k

VCO

GND

18

100pF

100pF

18

18

715

16

2

1

6

5

8

51

100pF

34

9

100pF

DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE

BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

CP

CE

POWER-DOWN CONTROL

S

IN

D

GND

LOOP

FILTER

ADG702

Figure 27. Local Oscillator Shutdown Circuit

LOW-PASS

FILTER

ADF4118

VCO190-1960T

18

100pF

18

100pF

CP

SERIAL

DIGITAL

NTERFACE

TCXO

OSC 3B1-13M0

100pF

51

18pF

1k

10k

6.8nF

18

POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS

ARE OMITTED FROM DIAGRAM FOR CLARITY.

AD9761

REFIO

FS ADJ

MODULATED

DIGITAL

DATA

QOUTB

IOUTA

IOUTB

QOUTA

LOW-PASS

FILTER

IBBP

QBBP

IBBP

QBBP

AD8346

LOIN

LOIP

VOUT

100pF

100pF

2k

0.1 F

100pF

680pF

Figure 28. Direct Conversion Transmitter Solution

The maximum allowable serial clock rate is 20 MHz. This means

that the maximum update rate possible for the device is 833 kHz or

one update every 1.2 microseconds. This is certainly more than

adequate for systems which will have typical lock times in hun-

dreds of microseconds.