PCF8523TSSLASH1 datasheet(47/75 Pages) NXP

47 / 75 page

PCF8523

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Product data sheet

Rev. 4 — 5 July 2012

47 of 74

NXP Semiconductors

PCF8523

Real-Time Clock (RTC) and calendar

[1]

Devices with other I2C-bus slave addresses can be produced on request.

After a START condition, the I2C slave address has to be sent to the PCF8523 device.

The R/W bit defines the direction of the following single or multiple byte data transfer. For

the format and the timing of the START condition (S), the STOP condition (P) and the

acknowledge bit (A) refer to the I2C-bus characteristics (see Ref. 12 on page 67). In the

write mode, a data transfer is terminated by sending either the STOP condition or the

START condition of the next data transfer.

Table 46.

I2C slave address byte

Slave address[1]

Bit

MSB

LSB

0R/W

Fig 32. Bus protocol for write mode

013aaa338

slave address

00h to 13h

0 to n

data bytes

write bit

START/

STOP

acknowledge

from PCF8523

acknowledge

from PCF8523

acknowledge

from PCF8523

P/S

Fig 33. Bus protocol for read mode

013aaa339

slave address

0 to n data bytes

DATA BYTE

LAST DATA BYTE

read bit

acknowledge

from PCF8523

acknowledge

from master

no acknowledge

slave address

00h to 13h

set register

address

read register

data

write bit

STOP

acknowledge

from PCF8523

acknowledge

from PCF8523

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