PCF8523USLASH12AASLASH1 datasheet(19/75 Pages) NXP

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PCF8523

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Product data sheet

Rev. 4 — 5 July 2012

19 of 74

NXP Semiconductors

PCF8523

Real-Time Clock (RTC) and calendar

An unreliable battery does not ensure data integrity during periods of backup battery

operation.

When VBAT drops below the threshold value Vth(bat)low, the following sequence occurs (see

Figure 11):

1. The battery low flag BLF is set logic 1

2. An interrupt is generated if the control bit BLIE (register Control_3) is enabled. The

interrupt remains active until the battery is replaced (BLF set logic 0) or when bit BLIE

is disabled (BLIE set logic 0)

3. The flag BLF (register Control_3) remains logic 1 until the battery is replaced. BLF

cannot be cleared using the interface. It is cleared automatically by the battery low

detection circuit when the battery is replaced

8.6 Time and date registers

Most of these registers are coded in the Binary Coded Decimal (BCD) format. BCD is

used to simplify application use. An example is shown for the array SECONDS in

Table 13.

Fig 11. Battery low detection behavior with bit BLIE set logic 1 (enabled)

013aaa323

internal power supply (= VBBS)

VBAT

BLF

Vth(bat)low

(= 2.5 V)

VBAT

VDD = VBBS

INT1

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