PCF8523USLASH12AASLASH1 datasheet(40/75 Pages) NXP

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PCF8523

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Product data sheet

Rev. 4 — 5 July 2012

40 of 74

NXP Semiconductors

PCF8523

Real-Time Clock (RTC) and calendar

8.9.5 Timer interrupt pulse

The timer interrupt is generated as a pulsed signal when TAM or TBM are set logic 1. The

pulse generator for the timer interrupt also uses an internal clock, but this time it is

dependent on the selected source clock for the timer and on the timer register value n. So,

the width of the interrupt pulse varies; see Table 43 and Table 44.

[1]

n = loaded timer register value. Timer stops when n = 0.

For timer B, interrupt pulse width is programmable via bit TBM (register

Tmr_CLKOUT_ctrl).

In this example, bit TAM is set logic 1 and the SF flag is not cleared after an interrupt.

Fig 22. Example for second interrupt when TAM = 1

In this example, bit TAM is set logic 0 and the SF flag is cleared after an interrupt.

Fig 23. Example for second interrupt when TAM = 0

013aaa331

seconds counter

minutes counter

INT1 when SIE enabled

SF when SIE enabled

013aaa332

seconds counter

minutes counter

INT1 when SIE enabled

SF when SIE enabled

Table 43.

Interrupt low pulse width for timer A

Pulse mode, bit TAM set logic 1.

Source clock (Hz)

Interrupt pulse width

n = 1[1]

n > 1[1]

4096

122

s

244

s

7.812 ms

15.625 ms

1⁄60

15.625 ms

1⁄3600

15.625 ms

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