MMDF3N06HD

5

Motorola TMOS Power MOSFET Transistor Device Data

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous drain–to–source voltage and

drain current that a transistor can handle safely when it is for-

ward biased. Curves are based upon maximum peak junc-

tion temperature and a case temperature (TC) of 25°C. Peak

repetitive pulsed power limits are determined by using the

thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal Resistance – Gen-

eral Data and Its Use.”

Switching between the off–state and the on–state may tra-

verse any load line provided neither rated peak current (IDM)

nor rated voltage (VDSS) is exceeded, and that the transition

time (tr, tf) does not exceed 10 µs. In addition the total power

averaged over a complete switching cycle must not exceed

(TJ(MAX) – TC)/(R

θJC).

A power MOSFET designated E–FET can be safely used

in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis-

sipated in the transistor while in avalanche must be less than

the rated limit and must be adjusted for operating conditions

differing from those specified. Although industry practice is to

rate in terms of energy, avalanche energy capability is not a

constant. The energy rating decreases non–linearly with an

increase of peak current in avalanche and peak junction tem-

perature.

Although many E–FETs can withstand the stress of drain–

to–source avalanche at currents up to rated pulsed current

(IDM), the energy rating is specified at rated continuous cur-

rent (ID), in accordance with industry custom. The energy rat-

ing must be derated for temperature as shown in the

accompanying graph (Figure 9). Maximum energy at cur-

rents below rated continuous ID can safely be assumed to

equal the values indicated.

Figure 8. Capacitance Variation

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Qg, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

1000

1.0

100

10

1.0

VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

1.0

1.5

2.0

2.5

0.5

0.55

0

0

2.0

4.0

6.0

8.0

ID = 3.0 A

TJ = 25°C

VGS

6.0

3.0

0

12

9.0

30

20

10

0

VDS

QT

Q1

Q2

Q3

10

16

–10

0

10

15

25

VGS

VDS

TJ = 25°C

1000

800

600

400

200

0

20

–5.0

5.0

Ciss

30

VDD = 30 V

ID = 3.0 A

VGS = 10 V

TJ = 25°C

Figure 9. Gate–to–Source and

Drain–to–Source Voltage versus Total Charge

Figure 10. Resistive Switching Time Variation

versus Gate Resistance

Figure 11. Diode Forward Voltage

versus Current

0.5

TJ = 25°C

VGS = 0 V

0.6

0.65

0.7

0.75

0.8

100

10

td(off)

1200

12

14

Ciss

Crss

Coss

5.0

2.0

11

8.0

4.0

1.0

10

7.0

td(on)

tr

tf