TMPR28051 datasheet(21/90 Pages) AGERE

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Data Sheet

August 1999

TMPR28051 STS-1/AU-3 (STM-0) Mapper

Lucent Technologies Inc.

Pin Information (continued)

Table 1. Pin Descriptions

* Iu indicates an internal pull-up; Id indicates an internal pull-down. All I/O not explicitly stated with a buffer type are 5 V TTL compatible; they will

tolerate 5 V at their inputs.

Symbol

Type*

Name/Description

47, 39, 38, 30,

29, 20, 19, 11,

10, 3, 206, 199,

198, 190, 175,

167, 166, 159,

154, 146, 145,

137, 136, 127,

126, 117, 115,

107

TCLK[1:28]

Transmit DS1/E1 Clock. DS1/E1 clock output. E1 signals can only

occupy TCLK[1:21].

46, 41, 37, 32,

28, 22, 18, 13, 9,

4, 205, 200, 197,

191, 174, 169,

165, 160, 153,

147, 143, 138,

134, 128, 124,

118, 114, 108

TDATA[1:28]

Transmit DS1/E1 Data. Transmit data output. E1 signals can only

occupy TDATA[1:21].

45, 42, 36, 33,

27, 23, 17, 14, 8,

5, 204, 201, 195,

192, 173, 170,

164, 161, 152,

148, 142, 139,

133, 129, 123,

119, 113, 109

RCLK[1:28]

Receive DS1/E1 Clock. Receive clock input. These pins have an

internal 20 k

Ω pull-up resistor. E1 signals can only occupy RCLK[1:21].

44, 43, 35, 34,

25, 24, 16, 15, 7,

6, 203, 202, 194,

193, 172, 171,

163, 162, 151,

149, 141, 140,

132, 131, 122,

120, 112, 110

RDATA[1:28]

Receive DS1/E1 Data. Receive data input. These pins have an inter-

nal 20 k

Ω pull-up resistor. E1 signals can only occupy RDATA[1:21].

102

DS1_E1N

DS1/E1 Input Identifier. If this pin is pulled high, the device will default

to DS1 to STS-1 mode and transmit 0s in the unused overhead bytes

and 00 in the SS bits of H1. If pulled low, the device will default to E1 to

AU-3 mode and transmit 1s in the unused overhead bytes and 10 in

the SS bits of H1. This default selection can be overridden by setting

TOVERRIDE and ROVERRIDE bits in registers 0x88 (bit 0) and 0x89

(bit 0), respectively. The seven VT Groups can then be individually pro-

grammed to carry either DS1 (TVTG-1. . . 7 = 1, RVTG-1. . . 7 = 1) or

E1 (TVTG-1. . . 7 = 0, RVTG-1. . . 7 = 0) signals.

101

DS1BLUECLK

DS1 Blue Signal Clock. In the event of a loss of input DS1 clock or an

unprovisioned DS1 output, this clock signal is used to generate the

DS1 blue signal (all 1s). This clock must be 1.544 MHz ± 32 ppm or 16

times this rate when using the digital jitter attenuator.

208

E1BLUECLK

E1 Blue Signal Clock. In the event of a loss of input E1 clock or an

unprovisioned E1 output, this clock signal is used to generate the E1

blue signal (all 1s). This clock must be 2.048 MHz ± 50 ppm or 16

times this rate when using the digital jitter attenuator.

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