ADAU1977WBCPZ-R7 datasheet(36/64 Pages) AD

36 / 64 page

ADAU1977

Data Sheet

Rev. A | Page 36 of 64

PLL CONTROL REGISTER

Address: 0x01, Reset: 0x41, Name: PLL_CONTROL

Table 27. Bit Descriptions for PLL_CONTROL

Bits

Bit Name

Settings

Description

Reset

Access

PLL_LOCK

PLL Lock Status. PLL lock status bit. When one PLL is locked.

0x0

PLL Not Locked

PLL Locked

PLL_MUTE

PLL Unlock Automute. When set to 1, mutes the ADC output if PLL

becomes unlocked.

0x1

No Automatic Mute on PLL Unlock

Automatic Mute with PLL Unlock

RESERVED

Reserved.

0x0

CLK_S

PLL Clock Source Select. Selecting input clock source for PLL.

0x0

MCLK Used for PLL Input

LRCLK Used for PLL Input; Only Supported for Sample Rates > 32 kHz

[2:0]

MCS

Master Clock Select. MCS bits determine the frequency multiplication

ratio of the PLL. It must be set based on the input MCLK frequency and

sample rate.

0x1

001

256 × fS MCLK for 32 kHz up to 48 kHz (see the PLL section for other

sample rates)

010

384 × fS MCLK for 32 kHz up to 48 kHz (see the PLL section for other

sample rates)

011

512 × fS MCLK for 32 kHz up to 48 kHz (see the PLL section for other

sample rates)

100

768 × fS MCLK for 32 kHz up to 48 kHz (see the PLL section for other

sample rates)

000

128 × fS MCLK for 32 kHz up to 48 kHz (see the PLL section for other

sample rates)

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