STM32F051C8T6 datasheet(14/104 Pages) STMICROELECTRONICS

14 / 104 page

Functional overview

STM32F051x

14/105

Doc ID 022265 Rev 3

3.5.3

Voltage regulator

The regulator has three operating modes: main (MR), low power (LPR) and power down.

●

MR is used in normal operating mode (Run)

●

LPR can be used in Stop mode where the power demand is reduced

●

Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode, providing high

impedance output.

3.5.4

Low-power modes

The STM32F051x family supports three low-power modes to achieve the best compromise

between low power consumption, short startup time and available wakeup sources:

●

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

●

Stop mode

Stop mode achieves very low power consumption while retaining the content of SRAM

and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the

HSE crystal oscillators are disabled. The voltage regulator can also be put either in

normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line

source can be one of the 16 external lines, the PVD output, RTC alarm, COMPx, I2C1,

USART1 or the CEC.

The I2C1, USART1 and the CEC can be configured to enable the HSI RC oscillator for

processing incoming data. If this is used, the voltage regulator should not be put in the

low-power mode but kept in normal mode.

●

Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a

rising edge on the WKUP pins, or an RTC alarm occurs.

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

3.6

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example on

failure of an indirectly used external crystal, resonator or oscillator).

STM32F051C8T6 데이터시트(PDF) 14 Page - STMicroelectronics

STM32F051C8T6 데이터시트(HTML) 14 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL