STM32F415ZG datasheet(139/186 Pages) STMICROELECTRONICS

139 / 186 page

DocID022063 Rev 4

139/186

STM32F415xx, STM32F417xx

Electrical characteristics

Asynchronous waveforms and timings

Figure 55 through Figure 58 represent asynchronous waveforms and Table 75 through

Table 78 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

•

AddressSetupTime = 1

•

AddressHoldTime = 0x1

•

DataSetupTime = 0x1

•

BusTurnAroundDuration = 0x0

In all timing tables, the THCLK is the HCLK clock period.

Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2)

Symbol

Parameter

Min

Max

Unit

tw(NE)

FSMC_NE low time

2THCLK–0.5 2 THCLK+1

tv(NOE_NE)

FSMC_NEx low to FSMC_NOE low

0.5

tw(NOE)

FSMC_NOE low time

2THCLK–2 2THCLK+ 2

th(NE_NOE)

FSMC_NOE high to FSMC_NE high hold time

tv(A_NE)

FSMC_NEx low to FSMC_A valid

4.5

th(A_NOE)

Address hold time after FSMC_NOE high

Data

FSMC_NE

FSMC_NBL[1:0]

FSMC_D[15:0]

tv(BL_NE)

t h(Data_NE)

FSMC_NOE

Address

FSMC_A[25:0]

tv(A_NE)

FSMC_NWE

tsu(Data_NE)

tw(NE)

ai14991c

w(NOE)

tv(NOE_NE)

t h(NE_NOE)

th(Data_NOE)

t h(A_NOE)

t h(BL_NOE)

tsu(Data_NOE)

FSMC_NADV(1)

t v(NADV_NE)

tw(NADV)

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