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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADE7953 데이터시트(PDF) 6 Page - Analog Devices |
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ADE7953 데이터시트(HTML) 6 Page - Analog Devices |
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6 / 68 page  ADE7953 Data Sheet Rev. A | Page 6 of 68 TIMING CHARACTERISTICS SPI Interface Timing VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted. Table 2. Parameter Description Min1 Max1 Unit tCS CS to SCLK edge 50 ns tSCLK SCLK period 200 ns tSL SCLK low pulse width 80 ns tSH SCLK high pulse width 80 ns tDAV Data output valid after SCLK edge 80 ns tDSU Data input setup time before SCLK edge 70 ns tDHD Data input hold time after SCLK edge 5 ns tDF Data output fall time 20 ns tDR Data output rise time 20 ns tSR SCLK rise time 20 ns tSF SCLK fall time 20 ns tDIS MISO disabled after CS rising edge 5 40 ns tSFS CS high after SCLK edge 0 ns tSFS_LK CS high after SCLK edge (when writing to COMM_LOCK bit) 1200 ns 1 Min and max values are typical minimum and maximum values. SPI Interface Timing Diagram LSB IN INTERMEDIATE BITS INTERMEDIATE BITS tSFS_LK tSFS tDIS tCS tSL tDF tSH tDHD tDAV tDSU tSR tSF tDR tSCLK MSB IN MOSI MISO SCLK CS MSB OUT LSB OUT Figure 2. SPI Interface Timing |
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