PIC12CE673 datasheet(42/130 Pages) MICROCHIP

42 / 130 page

PIC12C67X

DS30561C-page 42

 1997-2013 Microchip Technology Inc.

7.3

Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer, respectively (Figure 7-6). For simplicity, this

counter is being referred to as “prescaler” throughout

this data sheet. Note that there is only one prescaler

available which is mutually exclusively shared between

the Timer0 module and the Watchdog Timer. Thus, a

prescaler assignment for the Timer0 module means

that there is no prescaler for the Watchdog Timer, and

vice-versa.

The PSA and PS<2:0> bits (OPTION<3:0>) determine

the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (i.e., CLRF 1, MOVWF 1,

BSF

1,x

...., etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the Watchdog Timer. The pres-

caler is not readable or writable.

FIGURE 7-6:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

GP2/T0CKI/

T0SE

AN2/INT

CLKOUT (= FOSC/4)

SYNC

Cycles

TMR0 reg

8-bit Prescaler

8 - to - 1MUX

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS<2:0>

Note: T0CS, T0SE, PSA, PS<2:0> are (OPTION<5:0>).

PSA

WDT Enable bit

Data Bus

Set flag bit T0IF

on Overflow

PSA

T0CS

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