MPC823 datasheet(10/70 Pages) FREESCALE

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MPC823 ELECTRICAL SPECIFICATIONS

B40

A(6:31), TSIZ(0:1), RD/WR, BURST, Valid to CLKOUT Rising

Edge

9Ñ7Ñ7Ñ

B41

TS Valid to CLKOUT Rising Edge (Setup Time)

9Ñ7Ñ7Ñ

B42

CLKOUT Rising Edge to TS Valid (Hold Time)

2Ñ2Ñ2Ñ

B43

AS Negation to Memory Controller Signals Negation

NOTES:

The timing for BR output is relevant when the MPC823 is selected to work with the external bus arbiter.

The timing for BG output is relevant when the MPC823 is selected to work with the internal bus arbiter.

The setup times required for TA, TEA and BI are relevant only when they are supplied by an external device

(and not when the memory controller or the PCMCIA interface drive them).

The timing required for BR input is relevant when the MPC823 is selected to work with the internal bus arbiter.

The timing for BG input is relevant when the MPC823 is selected to work with the external bus arbiter.

The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA

input signal is asserted.

The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is

valid only under control of the UPM in the memory controller.

The timing B30 refers to CS when ACS = Ô00Õ and to WE(0:3) when CSNT = Ô0Õ.

The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings

speciÞed in B37 and B38 are speciÞed to enable the freeze of the UPM output signals.

The AS signal is considered asynchronous to the CLKOUT signal.

Figure 1. External Clock Timing Diagram

Table 1. Bus Operation Timing (Continued)

NUM

CHARACTERISTIC

25MHz

40MHz

50MHz

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

CLKOUT

Freescale Semiconductor, Inc.

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