TL16C554APNR datasheet(27/46 Pages) TI1

27 / 46 page

TL16C554A, TL16C554AI

ASYNCHRONOUS-COMMUNICATIONS ELEMENT

SLLS509E − AUGUST 2001 − REVISED JUNE 2010

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

modem-control register (MCR)

The MCR controls the interface with the modem or data set as described in Figure 19. The MCR can be written

and read. Outputs RTS and DTR are directly controlled by their control bits in this register. A high input asserts

a low signal (active) at the output terminals. MCR bits 0, 1, 2, 3, and 4 are shown as follows:

D Bit 0: When MCR0 is set, the DTR output is forced low. When MCR0 is cleared, the DTR output is forced

high. The DTR output of the serial channel may be input into an inverting line driver in order to obtain the

proper polarity input at the modem or data set.

D Bit1: When MCR1 is set, the RTS output is forced low. When MCR1 is cleared, the RTS output is forced

high. The RTS output of the serial channel may be input into an inverting line driver to obtain the proper

polarity input at the modem or data set.

D Bit 2: MCR2 has no effect on operation.

D Bit 3: When MCR3 is set, the external serial channel interrupt is enabled.

D Bit 4: MCR4 provides a local loopback feature for diagnostic testing of the channel. When MCR4 is set,

serial output TXx is set to the marking (high) state and SIN is disconnected. The output of the TSR is looped

back into the RSR input. The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected. The

four modem control output bits (DTR, RTS, OUT1, and OUT2) are internally connected to the four modem

control input bits (DSR, CTS, RI, and DCD), respectively. The modem control output terminals are forced

to their inactive (high) state. In the diagnostic mode, data transmitted is received by its own receiver. This

allows the processor to verify the transmit and receive data paths of the selected serial channel. Interrupt

control is fully operational; however, modem-status interrupts are generated by controlling the lower four

MCR bits internally. Interrupts are not generated by activity on the external terminals represented by those

four bits.

D Bit 5: This bit is the autoflow control enable (AFE). When set, the autoflow control is enabled, as described

in the detailed description.

The ACE flow control can be configured by programming bits 1 and 5 of the MCR, as shown in Table 7.

Table 7. ACE Flow Configuration

MSR BIT 5

(AFE)

MSR BIT 1

(RTS)

ACE FLOW CONFIGURATION

Auto-RTS and auto-CTS enabled (autoflow control enabled)

Auto-CTS only enabled

Auto-RTS and auto-CTS disabled

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