TL16C554A, TL16C554AI

ASYNCHRONOUS-COMMUNICATIONS ELEMENT

SLLS509E − AUGUST 2001 − REVISED JUNE 2010

32

POST OFFICE BOX 655303

Table 12. Baud Rates Using an 16-MHz Clock

BAUD RATE

DESIRED

DIVISOR (N) USED TO

GENERATE 16

× CLOCK

PERCENT ERROR DIFFERENCE

BETWEEN DESIRED AND ACTUAL

50

20000

0

75

13334

0.00

110

9090

0.01

134.5

7434

0.01

150

6666

0.01

300

3334

−0.02

600

1666

0.04

1200

834

−0.08

1800

554

0.28

2000

500

0.00

2400

416

0.16

3600

278

−0.08

4800

208

0.16

7200

138

0.64

9600

104

0.16

19200

52

0.16

38400

26

0.16

56000

18

−0.79

128000

8

−2.34

256000

4

−2.34

512000

2

−2.34

1000000

1

0.00

receiver

Serial asynchronous data is input into the RXx terminal. The ACE continually searches for a high-to-low

transition. When the transition is detected, a circuit is enabled to sample incoming data bits at the optimum point,

which is the center of each bit. The start bit is valid when RXx is still low at the sample point. Verifying the start

bits prevents the receiver from assembling a false data character due to a low-going noise spike on the RXx

input.

The number of data bits in a character is controlled by LCR0 and LCR1. Parity checking, generation, and polarity

are controlled by LCR3 and LCR4. Receiver status is provided in the LSR. When a full character is received,

including parity and stop bits, the data received indicator in LSR0 is set. In non-FIFO mode, the CPU reads the

RBR, which clears LSR0. If the character is not read prior to a new character transfer from RSR to RBR, an

overrun occurs and the overrun error status indicator is set in LSR1. If there is a parity error, the parity error is

set in LSR2. If a stop bit is not detected, a framing error indicator is set in LSR3.

In the FIFO mode, the data character and the associated error bits are stored in the receiver FIFO. If the data

in RXx is a symmetrical square wave, the center of the data cells occurs within

±3.125% of the actual center,

providing an error margin of 46.875%. The start bit can begin as much as one 16

× clock cycles prior to being

detected.