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TMS320 데이터시트(PDF) 52 Page - Texas Instruments |
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TMS320 데이터시트(HTML) 52 Page - Texas Instruments |
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52 / 70 page ![]() TMS320C25 SPRS010B — MAY 1987 — REVISED NOVEMBER 1990 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 52 HOLD timing (part A) CLKOUT1 CLKOUT2 STRB HOLD A15-A0 PS,DS, or IS R/W D15-D0 HOLDA FETCH EXECUTE td(C2H-H)† tdis(C1L-A) tdis(AL-A) td(C1L-AL) In In NN + 1 N + 2 Valid Valid N N + 1 -- -- N --2 N --1 N -- † HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur. |
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