MC68331TS datasheet(29/84 Pages) FREESCALE

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MC68331TS/D

Figure 9 Chip-Select Circuit Block Diagram

The following table lists allocation of chip-selects and discrete outputs on the pins of the MCU.

3.5.1 Chip-Select Registers

Pin assignment registers CSPAR0 and CSPAR1 determine functions of chip-select pins. These regis-

ters also determine port size (8- or 16-bit) for dynamic bus allocation.

A pin data register (PORTC) latches discrete output data.

Blocks of addresses are assigned to each chip-select function. Block sizes of 2 Kbytes to 1 Mbyte can

be selected by writing values to the appropriate base address register (CSBAR). Address blocks for

separate chip-select functions can overlap.

Chip-select option registers (CSORBT and CSOR[10:0]) determine timing of and conditions for asser-

tion of chip-select signals. Eight parameters, including operating mode, access size, synchronization,

and wait state insertion can be specified.

Initialization code often resides in a peripheral memory device controlled by the chip-select circuits. A

set of special chip-select functions and registers (CSORBT, CSBARBT) is provided to support bootstrap

operation.

Chip Select

Discrete Outputs

CSBOOT

—

CS0

—

CS1

—

BGACK

CS2

—

FC0

CS3

PC0

FC1

CS4

PC1

FC2

CS5

PC2

ADDR19

CS6

PC3

ADDR20

CS7

PC4

ADDR21

CS8

PC5

ADDR22

CS9

PC6

ADDR23

CS10

ECLK

CHIP SEL BLOCK

AVEC

GENERATOR

DSACK

GENERATOR

ASSIGNMENT

DATA

BASE ADDRESS REGISTER

TIMING

AND

CONTROL

ADDRESS COMPARATOR

OPTION COMPARE

OPTION REGISTER

AVEC

DSACK

BUS CONTROL

INTERNAL

SIGNALS

ADDRESS

Freescale Semiconductor, Inc.

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