MC68331TS datasheet(71/84 Pages) FREESCALE

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MC68331TS/D

Y = M111, where M is the logic state of the modmap (MM) bit in SIMCR.

6.2 Capture/Compare Unit

The capture/compare unit features three input capture channels, four output compare channels, and

one input capture/output compare channel (function selected by control register). These channels share

a 16-bit free-running counter (TCNT), which derives its clock from seven stages of a 9-stage prescaler

or from external clock input PCLK. This section, which is similar to the timer found on the MC68HC11F1,

also contains one pulse accumulator channel. The pulse accumulator logic includes its own 8-bit

counter and can operate in either event counting mode or gated time accumulation mode. Refer to the

following block diagrams of the GPT timer and prescaler.

Table 26 GPT Address Map

Access

Address

$YFF900

GPT MODULE CONFIGURATION (GPTMCR)

$YFF902

(RESERVED FOR TEST)

$YFF904

INTERRUPT CONFIGURATION (ICR)

$YFF906

PGP DATA DIRECTION (DDRGP)

PGP DATA (PORTGP)

$YFF908

OC1 ACTION MASK (OC1M)

OC1 ACTION DATA (OC1D)

$YFF90A

TIMER COUNTER (TCNT)

$YFF90C

PA CONTROL (PACTL)

PA COUNTER (PACNT)

$YFF90E

INPUT CAPTURE 1 (TIC1)

$YFF910

INPUT CAPTURE 2 (TIC2)

$YFF912

INPUT CAPTURE 3 (TIC3)

$YFF914

OUTPUT COMPARE 1 (TOC1)

$YFF916

OUTPUT COMPARE 2 (TOC2)

$YFF918

OUTPUT COMPARE 3 (TOC3)

$YFF91A

OUTPUT COMPARE 4 (TOC4)

$YFF91C

INPUT CAPTURE 4/OUTPUT COMPARE 5 (TI4/O5)

$YFF91E

TIMER CONTROL 1 (TCTL1)

TIMER CONTROL 2 (TCTL2)

$YFF920

TIMER MASK 1 (TMSK1)

TIMER MASK 2 (TMSK2)

$YFF922

TIMER FLAG 1 (TFLG1)

TIMER FLAG 2 (TFLG2)

$YFF924

FORCE COMPARE (CFORC)

PWM CONTROL C (PWMC)

$YFF926

PWM CONTROL A (PWMA)

PWM CONTROL B (PWMB)

$YFF928

PWM COUNT (PWMCNT)

$YFF92A

PWMA BUFFER (PWMBUFA)

PWMB BUFFER (PWMBUFB)

$YFF92C

GPT PRESCALER (PRESCL)

$YFF92E–

$YFF93F

NOT USED

Freescale Semiconductor, Inc.

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