MC68331MFC16 datasheet(51/84 Pages) FREESCALE

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MC68331TS/D

5 Queued Serial Module

The QSM contains two serial interfaces, the queued serial peripheral interface (QSPI) and the serial

communication interface (SCI).

Figure 12 QSM Block Diagram

5.1 Overview

The QSPI provides easy peripheral expansion or interprocessor communication through a full-duplex,

synchronous, three-line bus: data in, data out, and a serial clock. Four programmable peripheral chip-

select pins provide addressability for up to 16 peripheral devices. A self-contained RAM queue allows

up to 16 serial transfers of 8 to 16 bits each, or transmission of a 256-bit data stream without CPU in-

tervention. A special wraparound mode supports continuous sampling of a serial peripheral, with auto-

matic QSPI RAM updating, which makes the interface to A/D converters more efficient.

The SCI provides a standard nonreturn to zero (NRZ) mark/space format. It operates in either full- or

half-duplex mode. There are separate transmitter and receiver enable bits and dual data buffers. A

modulus-type baud rate generator provides rates from 64 to 524 kbaud with a 16.78-MHz system clock,

or 110 to 655 kbaud with a 20.97 MHz system clock. Word length of either 8 or 9 bits is software select-

able. Optional parity generation and detection provide either even or odd parity check capability. Ad-

vanced error detection circuitry catches glitches of up to 1/16 of a bit time in duration. Wakeup functions

allow the CPU to run uninterrupted until meaningful data is available.

An address map of the QSM is shown below. The “Access” column indicates which registers are acces-

sible only at the supervisor privilege level and which can be assigned to either the supervisor or user

privilege level, according to the value of the SUPV bit in the QSMCR.

QSPI

INTERFACE

LOGIC

SCI

MISO/PQS0

MOSI/PQS1

SCK/PQS2

PCS0/SS/PQS3

PCS1/PQS4

PCS2/PQS5

PCS3/PQS6

TXD/PQS7

RXD

QSM BLOCK

Freescale Semiconductor, Inc.

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