OMAP3530ECBBA datasheet(184/264 Pages) TI1

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6.5 Video Interfaces

6.5.1

Camera Interface

6.5.1.1 Parallel Camera Interface Timing

OMAP3530/25 Applications Processor

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

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The camera subsystem provides the system interfaces and the processing capability to connect raw, YUV,

or JPEG image sensor modules to the OMAP3530/25 device for video-preview, video-record, and

still-image-capture applications. The camera subsystem supports up to two simultaneous pixel flows but

only one of them can use the video processing hardware:

• PARALLEL: the parallel interface data must go through the video processing hardware.

The parallel camera interface is a 12-bit interface which can be used in two modes:

1. SYNC mode: progressive and interlaced image sensor modules for 8-, 10-, 11-, and 12-bit data. The

pixel clock can be up to 75 MHz in 12-bit mode. The pixel clock can be up to 130 MHz in 8-bit packed

mode.

2. ITU mode provides an ITU-R BT 656 compatible data stream with progressive image sensor modules

only in 8- and 10-bit configurations. The pixel clock can be up to 75 MHz.

6.5.1.1.1 SYNC Normal Mode

6.5.1.1.1.1 12-Bit SYNC Normal – Progressive Mode

Table 6-23 and Table 6-24 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-23).

Table 6-22. ISP Timing Conditions – 12-Bit SYNC Normal – Progressive Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

Input signal rise time

2.7

Input signal fall time

2.7

Output Condition

CLOAD

Output load capacitance

8.6

Table 6-23. ISP Timing Requirements – 12-Bit SYNC Normal – Progressive Mode(1)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP17

tc(pclk)

Cycle time(2), cam_pclk period

13.3

22.2

ISP18

tW(pclkH)

Typical pulse duration, cam_pclk high

0.5*P(3)

ISP18

tW(pclkL)

Typical pulse duration, cam_pclk low

0.5*P(3)

tdc(pclk)

Duty cycle error, cam_pclk

667

1111

tj(pclk)

Cycle jitter(4), cam_pclk

133

200

ISP19

tsu(dV-pclkH)

Setup time, cam_d[11:0] valid before cam_pclk rising

1.82

3.25

edge

ISP20

th(pclkH-dV)

Hold time, cam_d[11:0] valid after cam_pclk rising

1.82

3.25

edge

ISP21

tsu(dV-vsH)

Setup time, cam_vs valid before cam_pclk rising

1.82

3.25

edge

ISP22

th(pclkH-vsV)

Hold time, cam_vs valid after cam_pclk rising edge

1.82

3.25

ISP23

tsu(dV-hsH)

Setup time, cam_hs valid before cam_pclk rising

1.82

3.25

edge

(1)

The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2)

Related with the input maximum frequency supported by the ISP module.

(3)

P = cam_pclk period in ns

(4)

Maximum cycle jitter supported by cam_pclk input clock.

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

184

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