OMAP3530ECBBA datasheet(188/264 Pages) TI1

188 / 264 page

cam_xclki

cam_pclk

cam_vs

cam_hs

cam_d[7:0]

cam_wen

cam_fld

D(0)

D(n-3)

D(n-2)

D(n-1)

D(0)

D(1)

D(n-1)

ISP1

ISP2

ISP3

ISP4

ISP5

ISP6

ISP7

ISP8

ISP10

ISP4

ISP9

ISP11

030-059

ISP12

OMAP3530/25 Applications Processor

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

www.ti.com

Figure 6-24. ISP – 8-bit Packed SYNC – Progressive Mode(1)(2)(3)(4)(5)

(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable.

(2) The image sensor must be connected to the lower data lines and the unused lines must be grounded. However, it is possible to shift the

data to 0, 2, or 4 data internal lanes. The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode.

(3) Optionally, the data write to memory can be qualified by the external cam_wen signal. The cam_wen signal can be used as a external

memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. The polarity of

cam_fld is programmable.

(4) The camera module can pack 8-bit data into 16 bits. It doubles the maximum pixel clock. This mode can be particularly useful to transfer

a YCbCr data stream or compressed stream to memory at very high speed.

(5) In cam_xclki; I is equal to a or b.

6.5.1.1.1.3 12-Bit SYNC Normal – Interlaced Mode

Table 6-29 and Table 6-30 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-25).

Table 6-28. ISP Timing Conditions – 12-Bit SYNC Normal – Interlaced Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

Input signal rise time

2.7

Input signal fall time

2.7

Output Conditions

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

188

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