OMAP3530ECBBA datasheet(190/264 Pages) TI1

190 / 264 page

cam_xclki

cam_pclk

cam_vs

cam_hs

cam_d[11:0]

cam_wen

cam_fld

FRAME(0)

L(0)

L(n-1)

L(0)

D(0)

D(n-3)

D(n-2)

D(n-1)

D(0)

D(1)

D(2)

D(n-1)

PAIR

IMPAIR

ISP15

ISP16

ISP17

ISP18

ISP27

ISP19

ISP21

ISP22

ISP23

ISP20

ISP28

ISP24

ISP25

ISP26

030-057

OMAP3530/25 Applications Processor

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

www.ti.com

Figure 6-25. ISP – 12-Bit SYNC Normal – Interlaced Mode(1)(2)(3)(4)(5)(6)(7)(8)

(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output, the

signal length can be set.

(2) The parallel camera in SYNC mode supports interlaced image sensor modules and 8-, 10-, 11-, or 12-bit data.

(3) When the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be

grounded.

(4) It is possible to shift the data to 0, 2, or 4 data internal lanes.

(5) The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit

mode, and cam_d[11:0] in 12-bit mode.

(6) Optionally, the data write to memory can be qualified by the external cam_wen signal.

(7) The cam_wen signal can be used as a external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and

cam_wen signals are asserted.

(8) In cam_xclki; I is equal to a or b.

6.5.1.1.1.4 8-bit Packed SYNC – Interlaced Mode

Table 6-32 and Table 6-33 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-26).

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

190

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