FX3 datasheet(38/45 Pages) CYPRESS

38 / 45 page

CYUSB301X

Document Number: 001-52136 Rev. *N

Page 38 of 45

Reset Sequence

FX3’s hard reset sequence requirements are specified in this section.

Figure 19. Reset Sequence

Table 16. Reset and Standby Timing Parameters

Parameter

Definition

Conditions

Min (ms)

Max (ms)

tRPW

Minimum RESET# pulse width

Clock Input

–

Crystal Input

–

tRH

Minimum high on RESET#

–

tRR

Reset recovery time (after which Boot loader begins

firmware download)

Clock Input

–

Crystal Input

tSBY

Time to enter standby/suspend (from the time

MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set)

––

tWU

Time to wakeup from standby

Clock Input

–

Crystal Input

–

tWH

Minimum time before Standby/Suspend source may

be reasserted

–5

–

VDD

(core )

xVDDQ

XTALIN/

CLKIN

RESET #

Mandatory

Reset Pulse

Hard Reset

tRPW

tRh

Standby/

Suspend

Source

Standby/Suspend source Is asserted

(MAIN_POWER_EN/ MAIN_CLK_EN bit

is set)

Standby/Suspend

source Is deasserted

tSBY

tWU

XTALIN/ CLKIN must be stable

before exiting Standby/Suspend

tRR

tWH

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