FX3 datasheet(27/45 Pages) CYPRESS

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CYUSB301X

Document Number: 001-52136 Rev. *N

Page 27 of 45

Slave FIFO Interface

Synchronous Slave FIFO Sequence Description

■ FIFO address is stable and SLCS is asserted

■ SLOE is asserted. SLOE is an output-enable only, whose sole

function is to drive the data bus.

■ SLRD is asserted

■ The FIFO pointer is updated on the rising edge of the PCLK,

while the SLRD is asserted. This starts the propagation of data

from the newly addressed location to the data bus. After a

propagation delay of tco (measured from the rising edge of

PCLK), the new data value is present. N is the first data value

read from the FIFO. To have data on the FIFO data bus, SLOE

must also be asserted.

The same sequence of events is shown for a burst read.

Note For burst mode, the SLRD# and SLOE# are asserted

during the entire duration of the read. When SLOE# is asserted,

the data bus is driven (with data from the previously addressed

FIFO). For each subsequent rising edge of PCLK, while the

SLRD# is asserted, the FIFO pointer is incremented and the next

data value is placed on the data bus.

Figure 12. Synchronous Slave FIFO Read Mode

Synchronous Read Cycle Timing

PCLK

FIFO ADDR

tCYC

tCH

tCL

tAS

SLCS

SLRD

tRDS tRDH

SLOE

FLAGA

(dedicated thread Flag for An)

( 1 = Not Empty0= Empty)

tOELZ

Data Out

High-Z

Data

driven:DN(An)

tCDH

tOEZ

3- cycle latency

from addr to data

tCO

tOELZ

DN+1(An)

DN(Am)

DN+1(Am) DN+2(Am)

SLWR (HIGH)

tAH

FLAGB

(dedicated thread Flag for Am)

( 1 = Not Empty0= Empty)

2-cycle latency

from SLRD to data

tCFLG

2 cycle latency from

SLRD to FLAG

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