Z80C30 datasheet(39/81 Pages) ZILOG

39 / 81 page

PS011706-0511

Functional Descriptions

CMOS SCC Serial Communications Controller

Product Specification

The sequence for operation of the byte count and FIFO logic is to read the registers in the

following order. RR7, RR6, and RR1 (reading RR6 is optional). Additional logic prevents

the FIFO from being emptied by multiple reads from RR1. The read from RR7 latches the

FIFO empty/full status bit (D6) and steers the status multiplexer to read from the SCC

megacell instead of the status FIFO (since the status FIFO is empty). The read from RR1

allows an entry to be read from the FIFO (if the FIFO was empty, logic was added to pre-

vent a FIFO underflow condition).

Write Operation

When the end of an SDLC frame (EOF) is received and the FIFO is enabled, the contents

of the status and byte-count registers are loaded into the FIFO. The EOF signal is used to

increment the FIFO. If the FIFO overflows, RR7, bit D7 (FIFO Overflow) sets to indicate

the overflow. This bit and the FIFO control logic is reset by disabling and reenabling the

FIFO control bit (WR15, bit 02). For details of FIFO control timing during an SDLC

frame, see Figure 14.

Programming

The SCC contains Write registers in each channel that are programmed by the system sep-

arately to configure the functional personality of the channels.

Z85C30

In the SCC, the data registers are directly addressed by selecting a High on the D/C pin.

With all other registers (except WR0 and RR0), programming the Write registers requires

two Write operations and reading the read registers requires both a Write and a Read oper-

ation. The first write is to WR0 and contains three bits that point to the selected register.

Figure 14. SDLC Byte Counting Detail

Don’t Load

Counter On

1st Flag

Reset Byte

Counter Here

Reset

Byte Counter

Load Counter

Into FIFO and

Increment PTR

Internal Byte Strobe

Increments Counter

Reset

Byte Counter

Internal Byte Strobe

Increments Counter

Reset

Byte Counter

Load Counter

Into FIFO and

Increment PTR

Z80C30 데이터시트(PDF) 39 Page - Zilog, Inc.

Z80C30 데이터시트(HTML) 39 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

데이터시트 다운로드

링크 URL