| 전자부품 데이터시트 검색엔진 |
|
82563EB 데이터시트(PDF) 16 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
82563EB 데이터시트(HTML) 16 Page - Intel Corporation |
|
16 / 52 page ![]() 82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon 10 3.9 Reserved Signals 3.10 Voltage Control Pins Table 8. Test Signals Signal Name Pin Type Sub- Type Description RESERVED_NC 4 5 6 8 9 10 13 14 15 17 26 49 52 53 98 NC NC Reserved No Connect This pin should be left disconnected in normal operation. Connecting any of these pins may cause adverse effects and will not be supported. RESERVED_PD 82 I (T) TTL Reserved, Pull-down This signal used in the XOR chain. It should be pulled to VSS via a 1 to10 K Ω resistor. Table 9. Voltage Control Pins Signal Name Pin Type Sub- Type Description CTRL_18 25 A A 1.9V LVR Power Output Reference Voltage control for an external 1.9V PNP transistor in order to produce a linearly-regulated supply. If the 1.9V internal voltage regulator control circuit is not used, connect the CTRL_18 pin to VSS through a 10 K Ω resistor. CTRL_12 23 A A 1.2V LVR Power Output Reference Voltage control for an external 1.2V PNP transistor in order to produce a linearly-regulated supply. If the 1.2V internal voltage regulator control circuit is not used, connect the CTRL_12 pin to VSS through a 10 K Ω resistor. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |