SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(BUF)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

P

S

S

P

TMP451

SBOS686 – JUNE 2013

www.ti.com

TIMING DIAGRAMS

The TMP451 is two-wire and SMBus-compatible. Figure 15 to Figure 17 describe the timing for various

operations on the TMP451. Parameters for Figure 15 are defined in Table 8. Bus definitions are:

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line, from high to low, while the SCL line is high, defines

a start condition. Each data transfer initiates with a start condition. Denoted as S in Figure 15.

Stop Data Transfer: A change in the state of the SDA line from low to high while the SCL line is high defines a

stop condition. Each data transfer terminates with a repeated start or stop condition. Denoted as P in Figure 15.

Data Transfer: The number of data bytes transferred between a start and a stop condition is not limited and is

determined by the master device. The receiver acknowledges data transfer.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device that

acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line

is stable low during the high period of the acknowledge clock pulse. Take setup and hold times into account. On

a master receive, data transfer termination can be signaled by the master generating a not-acknowledge on the

last byte that has been transmitted by the slave.

Figure 15. Two-Wire Timing Diagram

Table 8. Timing Characteristics for Figure 15

FAST MODE

HIGH-SPEED MODE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

SCL Operating Frequency

0.001

0.4

0.001

2.5

MHz

Bus Free Time Between STOP and START Condition

1300

260

ns

Hold time after repeated START condition. After this period, the first clock

600

160

ns

is generated.

Repeated START Condition Setup Time

600

160

ns

STOP Condition Setup Time

600

160

ns

Data Hold Time

0

900

0

150

ns

Data Setup Time

100

30

ns

SCL Clock LOW Period

1300

260

ns

SCL Clock HIGH Period

600

60

ns

Data Fall/Rise Time

300

80

ns

SDA

Clock Fall/Rise Time

300

40

ns

SCL

for SCL

≤ 100kHz

1000

ns

18

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