PIC16F1825T-ESS datasheet(63/448 Pages) MICROCHIP

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 2010-2012 Microchip Technology Inc.

DS41440C-page 63

PIC16(L)F1825/1829

5.2.2.7

Internal Oscillator Clock Switch

Timing

When switching between the HFINTOSC, MFINTOSC

and the LFINTOSC, the new oscillator may already be

shut down to save power (see Figure 5-7). If this is the

case, there is a delay after the IRCF<3:0> bits of the

OSCCON register are modified before the frequency

selection takes place. The OSCSTAT register will

reflect the current active status of the HFINTOSC,

MFINTOSC and LFINTOSC oscillators. The sequence

of a frequency selection is as follows:

IRCF<3:0> bits of the OSCCON register are

modified.

If the new clock is shut down, a clock start-up

delay is started.

Clock switch circuitry waits for a falling edge of

the current clock.

The current clock is held low and the clock

switch circuitry waits for a rising edge in the new

clock.

The new clock is now active.

The OSCSTAT register is updated as required.

Clock switch is complete.

See Figure 5-7 for more details.

If the internal oscillator speed is switched between two

clocks of the same source, there is no start-up delay

before the new frequency is selected. Clock switching

time delays are shown in Table 5-1.

Start-up delay specifications are located in the

oscillator

tables

Section 30.0

“Electrical

Specifications”

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