AD1671

REV. B

–11–

Table III. Output Data Format

Input

Analog

Digital

Range

Coding

Input

l

Output

OTR

2

0 V to +2.5 V

Straight Binary

0000 0000 0000

1

0 V

0000 0000 0000

0

+2.5 V

1111 1111 1111

0

≥ +2.5003 V

1111 1111 1111

1

0 V to +5 V

Straight Binary

≤ –0.0006 V

0000 0000 0000

1

0 V

0000 0000 0000

0

+5 V

1111 1111 1111

0

≥ +5.0006 V

1111 1111 1111

1

–2.5 V to +2.5 V

Offset Binary

≤ –2.5006 V

0000 0000 0000

1

–2.5 V

0000 0000 0000

0

+2.5 V

1111 1111 1111

0

≥ +2.4994 V

1111 1111 1111

1

–5 V to +5 V

Offset Binary

≤ –5.0012 V

0000 0000 0000

1

–5 V

0000 0000 0000

0

+5 V

1111 1111 1111

0

≥ +4.9988 V

1111 1111 1111

1

–2.5 V to +2.5 V

Twos Complement

≤ –2.5006 V

1000 0000 0000

1

(Using MSB)

–2.5 V

1000 0000 0000

0

+2.5 V

0111 1111 1111

0

≥ +2.4994 V

0111 1111 1111

1

–5 V to +5 V

Twos Complement

≤ –5.0012 V

1000 0000 0000

1

(Using MSB)

–5 V

1000 0000 0000

0

+5 V

0111 1111 1111

0

≥ +4.9988 V

0111 1111 1111

1

NOTES

OUTPUT DATA FORMAT

The AD1671 provides both MSB and MSB outputs, delivering

data in positive true straight binary for unipolar input ranges

and positive true offset binary or twos complement for bipolar

input ranges. Straight binary coding is used for systems that ac-

cept positive-only signals. If straight binary coding is used with

bipolar input signals, a 0 V input would result in a binary output

of 2048. The application software would have to subtract 2048

to determine the true input voltage. Host registers typically per-

form math on signed integers and assume data is in that format.

Twos complement format minimizes software overhead which is

especially important in high speed data transfers, such as a

DMA operation. The CPU is not bogged down performing data

conversion steps, hence the total system throughput is increased.

OPTIONAL EXTERNAL REFERENCE

The AD1671 includes an onboard +2.5 V reference. The refer-

ence input pin (REF IN) can be connected to reference output

pin (REF OUT) or a standard external +2.5 V reference can be

selected to meet specific system requirements. Fast switching in-

put dependent currents are modulated at the reference input.

The reference input voltage can be held with the use of a capaci-

tor. To prevent the AD1671’s onboard reference from oscil-

lating when not connected to REF IN, REF OUT must be

connected to +5 V. It is possible to connect REF OUT to +5 V

due to its output circuit implementation which shuts down the

reference.

Figure 15 is the typical logic supply current vs. conversion rate

for various capacitor loads on the digital outputs.

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

1M

CONVERSION RATE – Hz

1k

10k

100k

CL = 50pF

CL = 30pF

CL = 0pF

Capacitive Loads on the Digital Outputs