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33FJ128GP708 데이터시트(PDF) 22 Page - Microchip Technology

부품명 33FJ128GP708
상세설명  dsPIC DSC High-Performance 16-Bit Digital Signal Controllers
PDF  90 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

33FJ128GP708 데이터시트(HTML) 22 Page - Microchip Technology

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dsPIC33F
DS70155C-page 20
Preliminary
© 2005 Microchip Technology Inc.
FIGURE 6-1:
OSCILLATOR SYSTEM BLOCK DIAGRAM
6.2
Power-on Reset
When a supply voltage is applied to the device, a
Power-on Reset is generated. A new Power-on Reset
event is generated if the supply voltage falls below the
device threshold voltage (VPOR). An internal POR
pulse is generated when the rising supply voltage
crosses the POR circuit threshold voltage.
6.3
Oscillator Start-up Timer/Stabilizer
(OST)
An Oscillator Start-up Timer (OST) is included to
ensure that a crystal oscillator (or ceramic resonator)
has started and stabilized. The OST is a simple, 10-bit
counter that counts 1024 TOSC cycles before releasing
the oscillator clock to the rest of the system. The time-
out period is designated as TOST. The TOST time is
involved every time the oscillator has to restart (i.e., on
Power-on Reset (POR) and wake-up from Sleep). The
Oscillator Start-up Timer is applied to the LP oscillator,
XT and HS modes (upon wake-up from Sleep, POR
and BOR) for the primary oscillator.
6.4
Watchdog Timer (WDT)
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software
malfunction. The WDT is a free-running timer that runs
off the on-chip LPRC oscillator, requiring no external
component. The WDT continues to operate even if the
main processor clock (e.g., the crystal oscillator) fails.
The Watchdog Timer can be “Enabled” or “Disabled”
either through a configuration bit (FWDTEN) in the
Configuration
register,
or
through
an
SFR
bit
(SWDTEN).
Any device programmer capable of programming
dsPIC® DSC devices (such as Microchip’s MPLAB®
PM3 Programmer) allows programming of this and
other configuration bits to the desired state. If enabled,
the WDT increments until it overflows or “times out”. A
WDT time-out forces a device Reset (except during
Sleep).
OSC1
Secondary
Oscillator
32 kHz
PLL
Module
Clock
Switching
and
Control
Block
OSC2
SOSCO
SOSCI
FOSC
Primary Osc
Secondary Osc
To Timer1
Internal Fast
RC (FRC)
Oscillator
Internal Low-Power
RC (LPRC)
Oscillator
Primary
Oscillator
FCY
Divide by 4



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