AD822 datasheet(18/88 Pages) AD

18 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 18 of 88

Mnemonic

Description

Bytes

Cycles

Branching

JMP @A+DPTR

Jump indirect relative to DPTR

RET

Return from subroutine

RETI

Return from interrupt

ACALL addr11

Absolute jump to subroutine

AJMP addr11

Absolute jump unconditional

SJMP rel

Short jump (relative address)

JC rel

Jump on carry equal to 1

JNC rel

Jump on carry equal to 0

JZ rel

Jump on accumulator = 0

JNZ rel

Jump on accumulator not equal to 0

DJNZ Rn,rel

Decrement register, JNZ relative

LJMP

Long jump unconditional

LCALL addr16

Long jump to subroutine

JB bit,rel

Jump on direct bit = 1

JNB bit,rel

Jump on direct bit = 0

JBC bit,rel

Jump on direct bit = 1 and clear

CJNE A,dir,rel

Compare A, direct JNE relative

CJNE A,#data,rel

Compare A, immediate JNE relative

CJNE Rn,#data,rel

Compare register, immediate JNE relative

CJNE @Ri,#data,rel

Compare indirect, immediate JNE relative

DJNZ dir,rel

Decrement direct byte, JNZ relative

Miscellaneous

NOP

No operation

1. One cycle is one clock.

2. Cycles of MOVX instructions are four cycles when they have 0 wait state. Cycles of MOVX instructions are 4 + n cycles when they have n wait states.

3. Cycles of LCALL instruction are three cycles when the LCALL instruction comes from interrupt.

OTHER SINGLE-CYCLE CORE FEATURES

Timer Operation

Timers on a standard 8052 increment by 1 with each machine

cycle. On the ADuC841/ADuC842/ADuC843, one machine

cycle is equal to one clock cycle; therefore the timers increment

at the same rate as the core clock.

ALE

The output on the ALE pin on a standard 8052 part is a clock at

1/6th of the core operating frequency. On the ADuC841/

ADuC842/ADuC843 the ALE pin operates as follows. For a

single machine cycle instruction,ALE is high for the first half of

the machine cycle and low for the second half. The ALE output

is at the core operating frequency. For a two or more machine

cycle instruction, ALE is high for the first half of the first

machine cycle and low for the rest of the machine cycles.

External Memory Access

There is no support for external program memory access on the

parts. When accessing external RAM, the EWAIT register may

need to be programmed to give extra machine cycles to MOVX

commands. This is to account for differing external RAM access

speeds.

EWAIT SFR

SFR Address

9FH

Power-On Default

00H

Bit Addressable

This special function register (SFR) is programmed with the

number of wait states for a MOVX instruction. This value can

range from 0H to 7H.

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