AD822 datasheet(31/88 Pages) AD

31 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 31 of 88

Initiating the Calibration in Code

When calibrating the ADC using ADCCON1, the ADC must be

set up into the configuration in which it will be used. The

ADCCON3 register can then be used to set up the device and to

calibrate the ADC offset and gain.

MOV ADCCON1,#08CH ;

ADC on; ADCCLK set

;to divide by 32,4

;acquisition clock

To calibrate device offset:

MOV ADCCON2,#0BH

;select internal AGND

MOV ADCCON3,#25H

;select offset calibration,

;31 averages per bit,

;offset calibration

To calibrate device gain:

MOV ADCCON2,#0CH

;select internal V

REF

MOV ADCCON3,#27H

;select offset calibration,

;31 averages per bit,

;offset calibration

To calibrate system offset, connect system AGND to an ADC

channel input (0).

MOV ADCCON2,#00H

;select external AGND

MOV ADCCON3,#25H

;select offset calibration,

;31 averages per bit

To calibrate system gain, connect system VREF to an ADC

channel input (1).

MOV ADCCON2,#01H

;select external V

REF

MOV ADCCON3,#27H

;select offset calibration,

;31 averages per bit,

;offset calibration

The calibration cycle time TCAL is calculated by the following

equation:

(

)

ACQ

CAL

NUMAV

ADCCLK

For an ADCCLK/FCORE divide ratio of 32, TACQ = 4 ADCCLK,

and NUMAV = 15, the calibration cycle time is

()

(

)

CAL

524288

In a calibration cycle, the ADC busy flag (Bit 7), instead of

framing an individual ADC conversion as in normal mode, goes

high at the start of calibration and returns to zero only at the

end of the calibration cycle. It can therefore be monitored in

code to indicate when the calibration cycle is completed. The

following code can be used to monitor the BUSY signal during

a calibration cycle:

WAIT:

MOV A, ADCCON3

;move ADCCON3 to A

JB ACC.7, WAIT

;If Bit 7 is set jump to

WAIT else continue

NONVOLATILE FLASH/EE MEMORY

The ADuC841/ADuC842/ADuC843 incorporate Flash/EE

memory technology on-chip to provide the user with nonvola-

tile, in-circuit, reprogrammable code and data memory space.

Flash/EE memory is a relatively recent type of nonvolatile

memory technology, which is based on a single transistor cell

architecture. Flash/EE memory combines the flexible in-circuit

reprogrammable features of EEPROM with the space efficient/

density features of EPROM as shown in Figure 37.

Because Flash/EE technology is based on a single transistor cell

architecture, a flash memory array, such as EPROM, can be

implemented to achieve the space efficiencies or memory densities

required by a given design. Like EEPROM, flash memory can be

programmed in-system at a byte level; it must first be erased,

the erase being performed in page blocks. Thus, flash memory

is often and more correctly referred to as Flash/EE memory.

EEPROM

TECHNOLOGY

EPROM

TECHNOLOGY

FLASH/EEMEMORY

TECHNOLOGY

IN-CIRCUIT

REPROGRAMMABLE

SPACE EFFICIENT/

DENSITY

Figure 37. Flash/EE Memory Development

Overall, Flash/EE memory represents a step closer to the ideal

memory device that includes nonvolatility, in-circuit program-

mability, high density, and low cost. Incorporated in the parts,

Flash/EE memory technology allows the user to update program

code space in-circuit, without the need to replace one-time

programmable (OTP) devices at remote operating nodes.

Flash/EE Memory and the ADuC841/ADuC842/ADuC843

The parts provide two arrays of Flash/EE memory for user

applications. Up to 62 kBytes of Flash/EE program space are

provided on-chip to facilitate code execution without any

external discrete ROM device requirements. The program

memory can be programmed in-circuit by using the serial

download mode provided, by using conventional third party

memory programmers, or via a user defined protocol that can

configure it as data if required.

Note that the following sections use the 62 kByte program space

as an example when referring to ULOAD mode. For the other

memory models (32 kByte and 8 kByte), the ULOAD space

moves to the top 8 kBytes of the on-chip program memory, i.e.,

for 32 kBytes, the ULOAD space is from 24 kBytes to 32 kBytes,

the kernel still resides in a protected space from 60 kBytes to

62 kBytes. There is no ULOAD space present on the 8 kBtye part.

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