AD9920ABBCZ datasheet(85/112 Pages) AD

부품명	AD9920ABBCZ

상세설명	12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator

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85 / 112 page

AD9920A

Rev. B | Page 85 of 112

VERTICAL TOGGLE POSITION PLACEMENT NEAR

COUNTER RESET

An additional consideration during the reset of the internal

counters is the vertical toggle position placement. There is a

region of 36 pixels prior to the internal counter reset in which

no toggles can take place.

Figure 107 shows this restriction for slave mode. The last 36 pixels

before the counters are reset cannot be used. In slave mode, the

counter reset is delayed with respect to VD/HD placement, so

the inhibited area is different than it is in master mode.

It is recommended that Pixel Location 0 not be used for any of

the toggle positions for the VSG and SUBCK pulses.

N-1

012

N-2

N-3

N-4

NO TOGGLE POSITIONS ALLOWED IN THIS AREA

N-5

N-6

N-7

N-8

N-9

N-10

N-11

N-12

N-13

N-32

N-33

N-34

N-35

NOTE:

TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 36 PIXELS OF PIXEL 0 LOCATION.

H-COUNTER

(PIXEL COUNTER)

H-COUNTER

RESET

Figure 107. Toggle Position Inhibited Area, Slave Mode

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