CC1050SLASHR datasheet(14/40 Pages) TI

14 / 40 page

CC1050

SWRS044

Page 14 of 40

Microcontroller Interface

Used in a typical system,

CC1050 will

interface

microcontroller.

This

microcontroller must be able to:

•

Program

CC1050 into different modes

via the 3-wire serial configuration

interface (PDATA, PCLK and PALE).

•

Interface to the synchronous data

signal interface (DI and DCLK).

•

Optionally the microcontroller can do

data encoding / decoding.

•

Optionally the microcontroller can

monitor the frequency lock status from

pin CHP_OUT (LOCK).

Connecting the microcontroller

The microcontroller uses 3 output pins for

the configuration interface (PDATA, PCLK

and PALE). PDATA should be a bi-

directional pin for data read-back. The DI

pin is used for data to be transmitted.

DCLK providing the data timing should be

connected to a microcontroller input.

Optionally another pin can be used to

monitor the LOCK signal (available at the

CHP_OUT pin). This signal is logic level

high when the PLL is in lock. See

Figure 6.

The microcontroller pins connected to

PDATA and PCLK can be used for other

purposes when the configuration interface

is not used. PDATA and PCLK are high

impedance inputs as long as PALE high.

PALE has an internal pull-up resistor and

should be left open (tri-stated by the

microcontroller) or set to a high level

during power down mode in order to

prevent a trickle current flowing in the pull-

up.

CC1050

PDATA

PCLK

PALE

CHP_OUT

(LOCK)

Micro-

controller

DCLK

(Optional)

CC1050

PDATA

PCLK

PALE

CHP_OUT

(LOCK)

Micro-

controller

DCLK

(Optional)

Figure 6. Microcontroller interface

Not Recommended for New Designs

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