MPC8306S datasheet(56/70 Pages) FREESCALE

56 / 70 page

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

Clocking

In addition, some of the internal units may be required to be shut off or operate at lower frequency than

the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped

The following table specifies which units have a configurable clock frequency. For detailed description,

refer to the “System Clock Control Register (SCCR)” section in the MPC8306S PowerQUICC II Pro

Integrated Communications Processor Family Reference Manual.

NOTE

Setting the clock ratio of these units must be performed prior to any access

to them.

The following table provides the maximum operating frequencies for the MPC8306S MAPBGA under

recommended operating conditions (see Table 2).

20.2

System PLL Configuration

The system PLL is controlled by the RCWL[SPMF] parameter. Table 49 shows the multiplication factor

encodings for the system PLL.

NOTE

System PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO

divider). The VCO divider needs to be set properly so that the System PLL

VCO frequency is in the range of 450–750 MHz.

As described in Section 20, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset

configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal

Table 47. Configurable Clock Units

Unit

Default Frequency

Options

I2C,SDHC, USB, DMA Complex

csb_clk

Off, csb_clk, csb_clk/2, csb_clk/3

Table 48. Operating Frequencies for MAPBGA

Characteristic1

Max Operating Frequency

Unit

e300 core frequency (core_clk)266

MHz

Coherent system bus frequency (csb_clk)133

MHz

QUICC Engine frequency (qe_clk)233

MHz

DDR2 memory bus frequency (MCLK)2

167

MHz

Local bus frequency (LCLKn)3

MHz

Notes:

1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting

csb_clk, MCLK, LCLK, and core_clk frequencies do not exceed their respective maximum or minimum operating

frequencies.

2. The DDR2 data rate is 2× the DDR2 memory bus frequency.

3. The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×

the csb_clk frequency (depending on RCWL[LBCM]).

MPC8306S 데이터시트(PDF) 56 Page - Freescale Semiconductor, Inc

MPC8306S 데이터시트(HTML) 56 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

데이터시트 다운로드

링크 URL