AMC7812SPAP datasheet(44/92 Pages) TI

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CH0-ALR

THERM-ALR

Alarm

Status

Bits

GALRBit

AMC7812

SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013

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Alarm Operation

The AMC7812 continuously monitors all analog inputs and temperatures in normal operation. When any input is

out of the specified range, an alarm triggers. When an alarm state occurs, the corresponding individual alarm bit

in the Status Register is set ('1'). Global alarm bit GALR in AMC Configuration Register 0 is the OR of individual

alarms, see Figure 94. When the ALARM-LATCH-DIS bit in the Alarm Control Register is cleared ('0'), the alarm

is latched. The global alarm bit (GALR) maintains '1' until the corresponding error condition[s] subside and the

alarm status is read. The alarm bits are referred to as being latched because they remain set until read by

software. This design ensures that out-of-limit events cannot be missed if the software is polling the device

periodically. All bits are cleared when reading the Status Register, and all bits are reasserted if the out-of limit

condition still exists on the next monitoring cycle, unless otherwise noted.

Figure 94. Global Alarm Bit

When the ALARM-LATCH-DIS bit in the Alarm Control Register is set ('1'), the alarm bit is not latched. The alarm

bit in the Status Register goes to '0' when the error condition subsides, regardless of whether the bit is read or

not. When GALR = '1', the ALARM pin goes low. When the GALR bit = '0', the ALARM is high (inactive).

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